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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "02/13/2019 10:02:49"
                                                                                
// Verilog Test Bench template for design : ip_pll
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ns
module tb_ip_pll;
// constants                                           
// general purpose registers
parameter	SYS_PERIOD = 20;	//定义系统时钟周期
// test vector input registers
reg sys_clk;
reg sys_rst_n;
// wires                                               
wire clk_25m;
wire clk_50m;
wire clk_100m;
wire clk_100m_180deg;

// assign statements (if any)                          
ip_pll i1 (
// port map - connection between master ports and signals/registers   
	.clk_25m(clk_25m),
	.clk_50m(clk_50m),
	.clk_100m(clk_100m),
	.clk_100m_180deg(clk_100m_180deg),
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n)
);
initial                                                
begin                                                  
	sys_clk <= 1'b0;
	sys_rst_n <= 1'b0;
	#(20*SYS_PERIOD)
	sys_rst_n <= 1'b1;
end 

always #(SYS_PERIOD/2) sys_clk <= ~sys_clk;                                                   
                                                   
endmodule

